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Freescale Semiconductor Advance Information
Document Number: MC33988 Rev. 4.0, 11/2009
Dual Intelligent High-current Self-protected Silicon High Side Switch (8.0m)
The 33988 is a dual self-protected 8.0m silicon switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. The 33988 is designed for harsh environments, and it includes self-recovery features. The device is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. Programming, control, and diagnostics are implemented via the Serial Peripheral Interface (SPI). A dedicated parallel input is available for alternate and pulse-width modulation (PWM) control of each output. SPI-programmable fault trip thresholds allow the device to be adjusted for optimal performance in the application. The 33988 is packaged in a power-enhanced 12 x 12 nonleaded PQFN package with exposed tabs. Features * * * * Dual 8.0m max high side switch with parallel input or SPI control 6.0V to 27V operating voltage with standby currents < 5.0A Output current monitoring with two SPI-selectable current ratios SPI control of over-current limit, over-current fault blanking time, output-OFF open load detection, output ON/OFF control, watchdog timeout, slew rates, and fault status reporting * SPI status reporting of overcurrent, open and shorted loads, overtemperature, under-voltage and over-voltage shutdown, fail-safe pin status, and program status * Enhanced -16V reverse polarity VPWR protection
VDD VDD VDD VPWR
33988
HIGH SIDE SWITCH
BOTTOM VIEW PNA SUFFIX 98ARL10521D 16-PIN PQFN
ORDERING INFORMATION
Device MC33988CPNA Temperature Range (TA) - 40C to 125C Package 16 PQFN
33988
VDD I/O I/O SO SCLK FS WAKE SI SCLK CS SO RST INO IN1 CSNS FSI GND LOAD HS0 LOAD HS1 VPWR GND
MCU
CS SI I/O I/O I/O A/D
Figure 1. 33988 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2009. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VPWR
VIC
VDD
IUP
Internal Regulator
Over-voltage Protection
CS SO
SPI 3.0 MHz Programmable Switch Delay 0ms -525ms Selectable Slew Rate Gate Drive
SI SCLK FS IN[0:1] RST WAKE
Selectable Over-current High Detection 50A or 37.5A Selectable Overcurrent Low Detection Blanking Time 0.15ms-155ms Selectable Over-current Low Detection 3.75A -12.5A Open Load Detection IDWN RDWN Over-temperature Detection
HS0
Logic
HS0
HS1
Programmable Watchdog 310ms-2500ms VIC IUP Selectable Output Current Recopy 1/10250 or 1/20500
HS1
FSI
GND
Figure 2. 33988 Simplified Internal Block Diagram
CSNS
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Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
WAKE CSNS SLCK VDD 15 HS1 RST FSI IN0 IN1
12 11 10 9
Figure 3. 33988 Pin Connections (Transparent Top View) Table 1. Pin Definitions Functional descriptions of many of these pins can be found in the Functional Pin Description section beginning on page 16.
Pin 1 2 3 4 5 6 7 8 9 Pin Name CSNS WAKE RST IN0 FS FSI CS SCLK SI Pin Function Output Input Input Input Output Input Input Input Input Formal Name Output Current Monitoring Wake Reset (Active Low) Direct Input 0 Fault Status (Active Low) Fail-Safe Input Chip Select (Active Low) Serial Clock Serial Input Definition This pin is used to output a current proportional to the designated HS0-1 output. This pin is used to input a Logic [1] signal so as to enable the watchdog timer function. This input pin is used to initialize the device configuration and fault registers, as well as place the device in a low-current Sleep mode. This input pin is used to directly control the output HS0. This is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. The value of the resistance connected between this pin and ground determines the state of the outputs after a watchdog timeout occurs. This input pin is connected to a chip select output of a master microcontroller (MCU). This input pin is connected to the MCU providing the required bit shift clock for SPI communication. This is a command data input pin connected to the SPI Serial Data Output of the MCU or to the SO pin of the previous device of a daisy chain of devices. This is an external voltage input pin used to supply power to the SPI circuit.
SO
CS 7
FS
SI
8
6
5
4
3
2
1
13 GND
14 VPWR
TRANSPARENT TOP VIEW
16 HS0
10
VDD
Input
Digital Drain Voltage (Power)
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PIN CONNECTIONS
Table 1. Pin Definitions (continued) Functional descriptions of many of these pins can be found in the Functional Pin Description section beginning on page 16.
Pin 11 12 13 14 15 16 Pin Name SO IN1 GND VPWR HS1 HS0 Pin Function Output Input Ground Input Output Output Formal Name Serial Output Direct Input 1 Ground Positive Power Supply High Side Output 1 High Side Output 0 Definition This output pin is connected to the SPI Serial Data Input pin of the MCU or to the SI pin of the next device of a daisy chain of devices. This input pin is used to directly control the output HS1. This pin is the ground for the logic and analog circuitry of the device. This pin connects to the positive power supply and is the source input of operational power for the device. Protected 8.0m high side power output to the load. Protected 8.0m high side power output to the load.
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted.
Rating ELECTRICAL RATINGS Operating Voltage Range Steady-State VDD Supply Voltage Input/Output Voltage(1) VDD VIN[0:1], RST, FSI CSNS, SI, SCLK,
CS, FS
Symbol
Value
Unit
VPWR -16 to 41 -0.3 to 5.5 - 0.3 to 7.0
V
V V
SO Output
Voltage(1)
VSO ICL(WAKE) ICL(CSNS) VHS
- 0.3 to VDD + 0.3 2.5 10
V mA mA V
WAKE Input Clamp Current CSNS Input Clamp Current Output Voltage Positive Negative Output Current(2) Output Clamp ESD Voltage Energy(3)
41 -15 IHS[0:1] ECL[0:1] VESD1 VESD3 750 500 30 0.37 A J V 2000
(4)
Human Body Model (HBM) Charge Device Model (CDM) Corner Pins (1, 12, 15, 16) All Other Pins (2, 11, 13, 14)
Notes 1. Exceeding this voltage limit may cause permanent damage to the device. 2. Continuous high side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current using package thermal resistance is required. 3. Active clamp energy using single-pulse method (L = 16mH, RL = 0, VPWR = 12V, TJ = 150C). 4. ESD1 testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100pF, RZAP = 1500); ESD3 testing is performed in accordance with the Charge Device Model (CDM), Robotic (Czap=4.0pF).
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted.
Rating THERMAL RATINGS Operating Temperature Ambient Junction Storage Temperature Thermal Resistance(5) Junction-to-Case Junction-to-Ambient Peak Package Reflow Temperature During Reflow(6), (7) RJC RJA TPPRT <1.0 30 Note 7 C TA TJ TSTG - 40 to 125 - 40 to 150 - 55 to 150 Symbol Value Unit
C
C C/W
Notes 5. Device mounted on a 2s2p test board according to JEDEC JESD51-2. 6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 7. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions 4.5V VDD 5.5V, 6.0V VPWR 27V, -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic POWER INPUT Battery Supply Voltage Range Full Operational VPWR Operating Supply Current Output ON, IHS0 and IHS1 = 0 A VPWR Supply Current Output OFF, Open Load Detection Disabled, WAKE > 0.7 x VDD, RST = VLOGIC HIGH Sleep State Supply Current (VPWR < 14V, RST < 0.5V, WAKE < 0.5V) TJ = 25C TJ = 85C VDD Supply Voltage VDD Supply Current No SPI Communication 3.0MHz SPI Communication VDD Sleep State Current Over-voltage Shutdown Threshold Over-voltage Shutdown Hysteresis Under-voltage Output Shutdown Under-voltage Hysteresis(9) Under-voltage Power-ON Reset Threshold(8) IDD(SLEEP) VPWR(OV) VPWR(OVHYS) VPWR(UV) VPWR(UVHYS) VPWR(UVPOR) VDD(ON) IDD(ON) - - - 28 0.2 5.0 - - - - - 32 0.8 5.5 0.25 - 1.0 5.0 5.0 36 1.5 6.0 - 5.0 A V V V V V IPWR(SLEEP) - - 4.5 - - 5.0 10 50 5.5 V mA IPWR(SBY) - - 5.0 A IPWR(ON) - - 20 mA VPWR 6.0 - 27 mA V Symbol Min Typ Max Unit
Notes 8. This applies to all internal device logic supplied by VPWR and assumes the external VDD supply is within specification. 9. This applies when the under-voltage fault is not latched (IN[0 : 1] = 0).
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.5V VDD 5.5V, 6.0V VPWR 27V, -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic POWER OUTPUT Output Drain-to-Source ON Resistance (IHS[0:1] = 7.5A, TJ = 25C) VPWR = 6.0V VPWR = 10V VPWR = 13V Output Drain-to-Source ON Resistance (IHS[0:1] = 7.5A, TJ = 150C) VPWR = 6.0V VPWR = 10V VPWR = 13V Output Source-to-Drain ON Resistance IHS[0:1] = 7.5A, TJ = 25C(10) VPWR = -12V Output Over-current High Detection Levels (9.0V < VPWR < 16V) SOCH = 0 SOCH = 1 Over-current Low Detection Levels (SOCL[2:0]) 000 001 010 011 100 101 110 111 Current Sense Ratio (9.0V < VPWR < 16V, CSNS < 4.5V) DICR D2 = 0 DICR D2 = 1 Current Sense Ratio (CSR0) Accuracy Output Current 2.5A 5.0A 6.25A 7.5A 10.0A 12.5A - 20 -14 -13 -12 -13 -13 - - - - - - 20 14 13 12 13 13 CSR0 CSR1 CSR0_ACC - - 1/10250 1/20500 - - % IOCL0 IOCL1 IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7 10.5 9.0 8.0 7.0 6.0 5.0 4.0 3.0 12.5 11.25 10.0 8.75 7.5 6.25 5.0 3.75 14.5 13.5 12.0 10.5 9.0 7.5 6.0 4.5 - IOCH0 IOCH1 40 30 50 37.5 60 45 A RDS(ON) - - 16.0 A RDS(ON) - - - - - - 20.4 13.6 13.6 m RDS(ON) - - - - - - 12.0 8.0 8.0 m m Symbol Min Typ Max Unit
Notes 10. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.5V VDD 5.5V, 6.0V VPWR 27V, -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic POWER OUTPUT (CONTINUED) Current Sense Ratio (CSR1) Accuracy Output Current 2.5A 5.0A 6.25A 7.5A 10.0A 12.5A Current Sense Clamp Voltage CSNS Open; IHS[0:1] = 15A Open Load Detection Current(11) Output Fault Detection Threshold Output Programmed OFF Output Negative Clamp Voltage 0.5A < IHS[0:1] < 2.0A, Output OFF Over-temperature Shutdown(12) Over-temperature Shutdown Hysteresis
(12)
Symbol
Min
Typ
Max
Unit
CSR1_ACC - 25 -19 -18 -17 -18 -18 VCL(CSNS) 4.5 IOLDC VOLD(THRES) 2.0 VCL - 20 TSD TSD(HYS) 160 5.0 - 175 - -15 190 20 3.0 4.0 30 6.0 - 7.0 100 - - - - - - 25 19 18 17 18 18
%
V
A V
V
C C
Notes 11. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. 12. Guaranteed by process monitoring. Not production tested.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 4.5V VDD 5.5V, 6.0V VPWR 27V, -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic CONTROL INTERFACE Input Logic High-voltage(13) Input Logic Low-voltage(13)
(14)
Symbol
Min
Typ
Max
Unit
VIH VIL VIN[0:1] (HYS) IDWN VRST CSO RDWN CIN VCL(WAKE)
0.7 VDD - 100 5.0 4.5 - 100 -
- - 600 - 5.0 - 200 4.0
- 0.2 VDD 1200 20 5.5 20 400 12
V V mV A V pF k pF V
Input Logic Voltage Hysteresis
Input Logic Pull-down Current (SCLK, IN, SI)
RST Input Voltage Range
SO, FS Tri-state Capacitance(15) Input Logic Pull-down Resistor (RST) and WAKE Input Capacitance(15) WAKE Input Clamp Voltage(16)
ICL(WAKE) < 2.5 mA WAKE Input Forward Voltage ICL(WAKE) = - 2.5mA SO High-state Output Voltage IOH = 1.0mA
FS, SO Low-state Output Voltage
7.0 VF(WAKE) - 2.0 VSOH 0.8 VDD VSOL - ISO(LEAK) - 5.0
-
14 V
-
- 0.3 V
-
- V
IOL = -1.6mA SO Tri-state Leakage Current
CS > 0.7 x VDD
0.2
0.4 A
0
5.0 A
Input Logic Pull-up
Current(17)
IUP 5.0 RFS RFSDIS RFSOFFOFF RFSONOFF RFSONON - 6.0 15 40 0 6.5 17 Infinite 1.0 7.0 19 - - 20
CS, VIN[0:1] > 0.7 x VDD
FSI Input Pin External Pull-down Resistance FSI Disabled, HS[0:1] Indeterminate FSI Enabled, HS[0:1] OFF FSI Enabled, HS0 ON, HS1 OFF FSI Enabled, HS[0:1] ON
k
Notes 13. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:1], and WAKE input signals. The WAKE and RST signals may be supplied by a derived voltage reference to VPWR. 14. 15. 16. 17. No hysteresis on FSI and wake pins. Parameter is guaranteed by processing monitoring but is not production tested. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested. The current must be limited by a series resistance when using voltages > 7.0V. Pull-up current is with CS OPEN. CS has an active internal pull-up to VDD.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 4.5V VDD 5.5V, 6.0V VPWR 27V, -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic POWER OUTPUT TIMING Output Rising Slow Slew Rate A (DICR D3 = 0)(18) 9.0V < VPWR < 16V Output Rising Slow Slew Rate B (DICR D3 = 0) 9.0V < VPWR < 16V Output Rising Fast Slew Rate A (DICR D3 = 9.0V < VPWR < 16V Output Rising Fast Slew Rate B (DICR D3 = 1) 9.0V < VPWR < 16V Output Falling Slow Slew Rate A (DICR D3 = 9.0V < VPWR < 16V Output Falling Slow Slew Rate B (DICR D3 = 9.0V < VPWR < 16V Output Falling Fast Slew Rate A (DICR D3 = 9.0V < VPWR < 16V Output Falling Fast Slew Rate B (DICR D3 = 9.0V < VPWR < 16V Output Turn-ON Delay Time in Fast/Slow Slew Rate DICR = 0, DICR = 1 Output Turn-OFF Delay Time in Slow Slew Rate Mode(21) DICR = 0 Output Turn-OFF Delay Time in Fast Slew Rate Mode(21) DICR = 1 Direct Input Switching Frequency (DICR D3 = 0) f PWM t DLY_FAST(OFF) 2.0 - 15 300 50 - Hz t DLY_SLOW(OFF) 5 57 125 s
(20) (19) (19)
Symbol
Min
Typ
Max
Unit
SRRA_SLOW 0.3 SRRB_SLOW 0.12 0.4 1.2 1.0 2.0
V/s
V/s
1)(18)
SRRA_FAST 0.6 SRRB_FAST 0.12 0.4 4.8 1.6 6.4
V/s
V/s
0)(18)
SRFA_SLOW 0.3 1.0 2.0
V/s
0)(19)
SRFB_SLOW 0.12 0.4 1.2
V/s
1)(18)
SRFA_FAST 1.2 3.2 6.4
V/s
1)(19)
SRFB_FAST 0.4 t DLY(ON) 1.0 8.0 30 1.4 4.8
V/s
s
s
Notes 18. Rise and Fall Slew Rates A measured across a 5.0 resistive load at high side output = 0.5V to VPWR - 3.5V. These parameters are guaranteed by process monitoring. 19. Rise and Fall Slew Rates B measured across a 5.0 resistive load at high side output = VPWR - 3.5V to VPWR - 0.5V. These parameters are guaranteed by process monitoring. 20. Turn-ON delay time measured from rising edge of IN[0:1] signal that would turn the output ON to VHS[0:1] = 0.5V with RL = 5.0 resistive load. 21. Turn-OFF delay time measured from falling edge that would turn the output OFF to VHS[0:1] = VPWR - 0.5V with RL = 5.0 resistive load.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 4.5V VDD 5.5V, 6.0V VPWR 27V, -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic POWER OUTPUT TIMING (CONTINUED) Overcurrent Detection Blanking Time (OCLT [1:0]) 00 01 10 11 Overcurrent High Detection Blanking Time CS to CSNS Valid Time
(22)
Symbol
Min
Typ
Max
Unit
ms
t OCL0 t OCL1 t OCL2 t OCL3 t OCH t CNSVAL t OSD0 t OSD1 t OSD2 t OSD3 t OSD4 t OSD5 t OSD6 t OSD7 t OSD0 t OSD1 t OSD2 t OSD3 t OSD4 t OSD5 t OSD6 t OSD7 t WDTO0 t WDTO1 t WDTO2 t WDTO3
108 7.0 0.8 0.08 1.0 -
155 10 1.2 0.15 10 -
202 13 1.6 0.25 20 10 s s ms
HS1 Switching Delay Time (OSD[2:0]) 000 001 010 011 100 101 110 111 HS0 Switching Delay Time (OSD[2:0]) 000 001 010 011 100 101 110 111 Watchdog Timeout (WD [1:0])(23) 00 01 10 11 434 207 1750 875 620 310 2500 1250 806 403 3250 1625 - - 110 110 220 220 330 330 0 0 150 150 300 300 450 450 - - 190 190 380 380 570 570 - 55 110 165 220 275 330 385 0 75 150 225 300 375 450 525 - 95 190 285 380 475 570 665
ms
ms
Notes 22. Time necessary for the CSNS to be within 5% of the targeted value. 23. Watchdog timeout delay measured from the rising edge of WAKE to RST from a sleep state condition to output turn-ON with the output driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured watchdog timeouts.
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 4.5V VDD 5.5V, 6.0V VPWR 27V, -40C TA 125C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic SPI INTERFACE CHARACTERISTICS Recommended Frequency of SPI Operation Required Low State Duration for
RST(24)
(25)
Symbol
Min
Typ
Max
Unit
f SPI
- - - - - - - - - -
- 50 - - 50 - - 50 25 25
3.0 350 300 5.0 167 167 167 167 83 83
MHz ns ns s ns ns ns ns ns ns ns
t WRST
t CS
Rising Edge of CS to Falling Edge of CS (Required Setup Time)
Rising Edge of RST to Falling Edge of CS (Required Setup Time)(25) Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) Required High State Duration of SCLK (Required Setup Time)(25) Required Low State Duration of SCLK (Required Setup Time)
(25) (25)
t ENBL t LEAD t WSCLKh t WSCLKl t LAG t SI(SU) t SI(HOLD) t RSO
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)(25) SI to Falling Edge of SCLK (Required Setup Falling Edge of SCLK to SI (Required Setup SO Rise Time CL = 200pF SO Fall Time CL = 200pF SI, CS, SCLK, Incoming Signal Rise Time(26) SI, CS, SCLK, Incoming Signal Fall Time(26) Time)(26) Time)(26)
-
25
50 ns
t FSO
- 25 - - - 65 50 50 50 145 145
t RSI t RSI t SO(EN) t SO(DIS) t VALID
- - - -
ns ns ns ns ns
Time from Falling Edge of CS to SO Low-impedance(27) Time from Rising Edge of CS to SO High-impedance(28)
Time from Rising Edge of SCLK to SO Data Valid(29) 0.2 x VDD SO 0.8 x VDD, CL = 200pF Notes 24. 25. 26. 27. 28. 29.
-
65
105
RST low duration measured with outputs enabled and going to OFF or disabled condition. Maximum setup time required for the 33988 is the minimum guaranteed time needed from the microcontroller. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for output status data to be available for use at SO. 1.0k on pull-up on CS. Time required for output status data to be terminated at SO. 1.0k on pull-up on CS. Time required to obtain valid data out from SO following the rise of SCLK.
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
TIMING DIAGRAMS
CS
VPWR VPWR VPWR - -0.5V VPWR 0.5V VVPWR-3.5V PWR - 3V
SR SRrB RB_SLOW & SRRB_FAST
SRfB SRFB_SLOW & SRFB_FAST SRfA SRFA_SLOW & SRFA_FAST
SRRA_SLOW & SRRA_FAST SRrA
HS
0.5V
0.5V t DLY_SLOW(OFF) & tDLY_FAST(OFF) Tdly(off)
t DLY(ON) Tdly(on)
Figure 4. Output Slew Rate and Time Delays
IOCHx
Load Current IOCLx t OCH Time t OCLx Figure 5. Overcurrent Shutdown
IOCH0 IOCH1 IOCL0
IOCL1
Load Current
IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7
Time
t OCHx t OCL3 t OCL2 t OCL1 t OCL0
Figure 6. Over-current Low and High Detection
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
Figure 6 illustrates the over-current detection level (IOCLX, IOCHX) the device can reach for each over-current detection blanking time (tOCHX, tOCLX):
* During tOCHX, the device can reach up to IOCH0 overcurrent level. * During tOCL3 or tOCL2 or tOCL1 or tOCL0, the device can be programmed to detect up to IOCL0.
VIH V
IH
RSTB RST
0.2 x 0.2 VDDVDD
TwRSTB
VIL TCSB t CS
VIL
t WRST
t ENBL
TENBL
0.7 x VDD 0.7VDD CS CSB 0.2 x VDD 0.7VDD tTlead LEAD t WSCLKh TwSCLKh t RSI
TrSI
VIH V
IH
VIL V
IL
SCLK SCLK
0.7 x VDD 0.7VDD 0.2 x VDD
0.2VDD
t LAG Tlag
VIH VIH VIL V
t TSIsu SI(SU)
t WSCLKl TwSCLKl
IL
t SI(HOLD) TSI(hold)
TfSI t FSI VIH V
IH
SI SI
Don't Care
0.7 x VDD 0.7 VDD 0.2VDD 0.2 x VDD
Valid
Don't Care
Valid
Don't Care
VIH VIL
Figure 7. Input Timing Switching Characteristics
t RSI
t FSI
TrSI
3.5V 3.5V
TfSI VOH VOH 50% 1.0V 1.0V VOL VOL
SCLK SCLK
t SO(EN)
TdlyLH
SO SO
0.7 x VDD VDD
VOH VOH VOL VOL
0.2 VDD DD 0.2 x V TrSO t RSO TVALID t VALID
Low-to-High Low to High
SO
SO
0.7 x V High to Low High-to-Low 0.7 VDD DD
TfSO t FSO
VOH VOH
TdlyHL
t SO(DIS)
0.2VDD 0.2 x VDD
VOL VOL
Figure 8. SCLK Waveform and Valid SO Data Delay Time
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33988 is a dual self-protected 8.0m silicon switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. The 33988 is designed for harsh environments, and includes self-recovery features. The device is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. Programming, control, and diagnostics are implemented via the Serial Peripheral Interface (SPI). A dedicated parallel input is available for alternate and Pulse Width Modulation (PWM) control of each output. SPI-programmable fault trip thresholds allow the device to be adjusted for optimal performance in the application. The 33988 is packaged in a power-enhanced 12 x 12 nonleaded PQFN package with exposed tabs.
FUNCTIONAL PIN DESCRIPTION
OUTPUT CURRENT MONITORING (CSNS)
This pin is used to output a current proportional to the designated HS0-1 output. That current is fed into a groundreferenced resistor and its voltage is monitored by an MCU's A/D. The channel to be monitored is selected via the SPI. This pin can be tri-stated through the SPI.
watchdog timeout occurs. Depending on the resistance value, either all outputs are OFF, ON, or the output HS0 only is ON. When the FSI pin is connected to GND, the watchdog circuit and fail-safe operation are disabled. This pin incorporates an active internal pull-up current source.
CHIP SELECT (CS)
This input pin is connected to a chip select output of a master microcontroller (MCU). The MCU determines which device is addressed (selected) to receive data by pulling the CS pin of the selected device Logic LOW, enabling SPI communication with the device. Other unselected devices on the serial link having their CS pins pulled-up Logic HIGH disregard the SPI communication data sent. This pin incorporates an active internal pull-up current source.
WAKE (WAKE)
This pin is used to input a Logic [1] signal so as to enable the watchdog timer function. An internal clamp protects this pin from high damaging voltages when the output is current limited with an external resistor. This input has a passive internal pull-down.
RESET (RST)
This input pin is used to initialize the device configuration and fault registers, as well as place the device in a lowcurrent Sleep mode. The pin also starts the watchdog timer when transitioning from Logic LOW to Logic HIGH. This pin should not be allowed to be Logic HIGH until VDD is in regulation. This pin has a passive internal pull-down.
SERIAL CLOCK (SCLK)
This input pin is connected to the MCU providing the required bit shift clock for SPI communication. It transitions one time per bit transferred at an operating frequency, fSPI, defined by the communication interface. The 50 percent duty cycle CMOS-level serial clock signal is idle between command transfers. The signal is used to shift data into and out of the device. This input has an active internal pull-down current source.
DIRECT IN 0 & 1 (INx)
This input pin is used to directly control the output HS0 and 1. This input has an active internal pull-down current source and requires CMOS logic levels. This input may be configured via the SPI.
SERIAL INPUT (SI)
This is a command data input pin connected to the SPI Serial Data Output of the MCU or to the SO pin of the previous device of a daisy chain of devices. The input requires CMOS logic-level signals and incorporates an active internal pull-down current source. Device control is facilitated by the input's receiving the MSB first of a serial 8-bit control command. The MCU ensures data is available upon the falling edge of SCLK. The logic state of SI present upon the rising edge of SCLK loads that bit command into the internal command shift register.
FAULT STATUS (FS)
This is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. When a device fault condition is detected, this pin is active LOW. Specific device diagnostic faults are reported via the SPI SO pin.
FAIL-SAFE INPUT (FSI)
The value of the resistance connected between this pin and ground determines the state of the outputs after a
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
DIGITAL DRAIN VOLTAGE (VDD)
This is an external voltage input pin used to supply power to the SPI circuit. In the event VDD is lost, an internal supply provides power to a portion of the logic, ensuring limited functionality of the device. All device configuration registers are reset.
is asserted Logic LOW. The generated SO output signals are CMOS logic levels. SO output data is available on the falling edge of SCLK and transitions immediately on the rising edge of SCLK.
POSITIVE POWER SUPPLY (VPWR)
This pin connects to the positive power supply and is the source input of operational power for the device. The VPWR pin is a backside surface mount tab of the package.
SERIAL OUTPUT (SO)
This output pin is connected to the SPI Serial Data Input pin of the MCU or to the SI pin of the next device of a daisy chain of devices. This output will remain tri-stated (highimpedance OFF condition) so long as the CS pin of the device is Logic HIGH. SO is only active when the CS pin of the device
HIGH-SIDE OUTPUT 0 & 1 (HSx)
This pin protects 8.0m high-side power output to the load.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
POWER SUPPLY MCU INTERFACE AND OUTPUT CONTROL SPI INTERFACE
MCU INTERFACE
SELF-PROTECTED HIGH SIDE SWITCH HS [0:1]
PARALLEL CONTROL INPUTS
Figure 9. Functional Internal Block Diagram
POWER SUPPLY
The 33988 is designed to operate from 4.0V to 28V on the VPWR pin. Characteristics are provided from 6.0V to 20V for the device. The VPWR pin supplies power to internal regulator, analog, and logic circuit blocks. The VDD supply is used for Serial Peripheral Interface (SPI) communication in order to configure and diagnose the device. This IC architecture provides a low quiescent current sleep mode. Applying VPWR and VDD to the device will place the device in the Normal mode. The device will transit to Fail-safe mode in case of failures on the SPI (watchdog timeout).
load disconnections and short-circuit fault conditions. The HS[0:1] outputs are actively clamped during a turn-off of inductive loads.
MCU INTERFACE AND OUTPUT CONTROL
In Normal mode, the loads are controlled directly from the MCU through the SPI. With a dedicated SPI command, it is possible to independently turn on and off several loads that are PWM'd at the same frequency, and duty cycles with only one PWM signal. An analog feedback output provides a current proportional to each load current. The SPI is used to configure and to read the diagnostic status (faults) of the high side output. The reported fault conditions are: open load, short-circuit to ground (OCLO-resistive and OCHI-severe short-circuit), thermal shutdown, and under/over-voltage. In Fail-safe mode, the loads are controlled with dedicated parallel input pins. The device is configured in default mode.
HIGH-SIDE SWITCH: HS[0:1]
Those pins are the high side outputs controlling multiple automotive loads with high inrush current, as well as motors and all types of resistive and inductive loads. This N-channel MOSFET with 8m RDS(ON), is self-protected and each Nchannel presents extended diagnostics in order to detect
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
The 33988 has four operating modes: Sleep, Normal, Fault, and Fail-safe. Table 5 summarizes details contained in succeeding paragraphs. Table 5. Fail-Safe Operation and Transitions to Other 33988 Modes
Mode FS WAKE RST WDTO Comments
Sleep Normal Fault
x 1 0 0
0 x 1 x 0 1 1
0 1 x 1 1 1 0
x No No
Device is in Sleep mode. All outputs are OFF. Normal mode. Watchdog is active if enabled. The device is currently in Fault mode. The faulted output(s) is (are) OFF. Watchdog has timed out and the device is in Failsafe mode. The outputs are as configured with the RFS resistor connected to FSI. RST and WAKE must be transitioned to Logic [0] simultaneously to bring the device out of the Failsafe mode or momentarily tied the FSI pin to ground.
Failsafe
1 1 1
Yes
transitions from Logic [0] to Logic [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance that limits the internal clamp current according to the specification. The watchdog timeout is a multiple of an internal oscillator and is specified in Table 14. As long as the WD bit (D7) of an incoming SPI message is toggled within the minimum watchdog timeout period (WDTO), based on the programmed value of the WDR the device will operate normally. If an internal watchdog timeout occurs before the WD bit, the device will revert to a Fail-safe mode until the device is reinitialized. During the Fail-safe mode, the outputs will be ON or OFF depending upon the resistor RFS connected to the FSI pin, regardless of the state of the various direct inputs and modes (Table 6). In this mode, the SPI register content is retained except for over-current high and low detection levels and timing, which are reset to their default value (SOCL, SOCH, and OCLT). Then the watchdog, over-voltage, overtemperature, and over-current circuitry (with default value) are fully operational. Table 6. Output State During Fail-safe Mode
RFS (k) High Side State
0 6.0 17 Open
Fail-safe mode Disabled Both HS0 and HS1 OFF HS0 ON, HS1 OFF Both HS0 and HS1 ON
x = Don't care.
SLEEP MODE
The default mode of the 33988 is the Sleep mode. This is the state of the device after first applying battery voltage (VPWR), prior to any I/O transitions. This is also the state of the device when the WAKE and RST are both Logic [0]. In the Sleep mode, the output and all unused internal circuitry, such as the internal 5.0 V regulator, are off to minimize current draw. In addition, all SPI-configurable features of the device are as if set to Logic [0]. The device will transition to the Normal or Fail-safe operating modes based on the WAKE and RST inputs as defined in Table 5.
The Fail-safe mode can be detected by monitoring the WDTO bit D2 of the WD register. This bit is Logic [1] when the device is in Fail-safe mode. The device can be brought out of the Fail-safe mode by transitioning the WAKE and RST pins from Logic [1] to Logic [0] or forcing the FSI pin to Logic [0]. Table 5 summarizes the various methods for resetting the device from the latched Fail-safe mode. If the FSI pin is tied to GND, the Watchdog Fail-safe operation is disabled.
NORMAL MODE
The 33988 is in Normal mode when: * VPWR is within the normal voltage range. * RST pin is Logic [1]. * No fault has occurred.
LOSS OF VDD
If the external 5.0V supply is not within specification, or even disconnected, all register content is reset. The two outputs can still be driven by the direct inputs IN 1:IN0. The 33988 uses the battery input to power the output MOSFETrelated current sense circuitry and any other internal logic providing Fail-safe device operation with no VDD supplied. In this state, the watchdog, over-voltage, over-temperature, and over-current circuitry are fully operational with default values.
FAIL-SAFE AND WATCHDOG
If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE or RST input pin
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Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSIS FEATURES
FAULT MODE
The 33988 indicates the following faults as they occur by driving the FS pin to Logic [0]: * Over-temperature fault * Open load fault * Over-current fault (high and low) * Over-voltage and under-voltage fault
The FS pin will automatically return to Logic [1] when the fault condition is removed, except for over-current and in some cases under-voltage. Fault information is retained in the fault register and is available (and reset) via the SO pin during the first valid SPI communication (refer to Table 16).
PROTECTION AND DIAGNOSIS FEATURES
OVER-TEMPERATURE FAULT (NON-LATCHING)
The 33988 incorporates over-temperature detection and shutdown circuitry in each output structure. Overtemperature detection is enabled when an output is in the ON state. For the output, an over-temperature fault (OTF) condition results in the faulted output turning OFF until the temperature falls below the TSD(HYS). This cycle will continue indefinitely until action is taken by the MCU to shut OFF the output, or until the offending load is removed. When experiencing this fault, the OTF fault bit will be set in the status register and cleared after either a valid SPI read or a power reset of the device.
report any under-voltage fault condition and the output state will not be changed as long as the battery voltage does not drop any lower than 2.5V.
OPEN LOAD FAULT (NON-LATCHING)
The 33988 incorporates open load detection circuitry on each output. Output open load fault (OLF) is detected and reported as a fault condition when that output is disabled (OFF). The open load fault is detected and latched into the status register after the internal gate voltage is pulled low enough to turn OFF the output. The OLF fault bit is set in the status register. If the open load fault is removed, the status register will be cleared after reading the register. The open load protection can be disabled trough SPI (bit OL_dis). It is recommended to disable the open load
OVER-VOLTAGE FAULT (NON-LATCHING)
The 33988 shuts down the output during an over-voltage fault (OVF) condition on the VPWR pin. The output remains in the OFF state until the over-voltage condition is removed. When experiencing this fault, the OVF fault bit is set in the bit OD1 and cleared after either a valid SPI read or a power reset of the device. The over-voltage protection and diagnostic can be disabled trough SPI (bit OV_dis).
detection circuitry (OL_dis bit sets to logic [1]) in case of permanent open load fault condition.
OVER-CURRENT FAULT (LATCHING)
The device has eight programmable over-current low detection levels (IOCL) and two programmable over-current high detection levels (IOCH) for maximum device protection. The two selectable, simultaneously active over-current detection levels, defined by IOCH and IOCL, are illustrated in Figure 6. The eight different over-current low detect levels (IOCL0 : IOCL7) are likewise illustrated in Figure 6. If the load current level ever reaches the selected overcurrent low detect level and the over-current condition exceeds the programmed over-current time period (tOCx), the device will latch the effected output OFF. If at any time the current reaches the selected IOCH level, then the device will immediately latch the fault and turn OFF the output, regardless of the selected tOCL driver. For both cases, the device output will stay off indefinitely until the device is commanded OFF and then ON again.
UNDER-VOLTAGE SHUTDOWN (LATCHING OR NON-LATCHING)
The output(s) will latch off at some battery voltage below 6.0 V. As long as the VDD level stays within the normal specified range, the internal logic states within the device will be sustained. In the case where the battery voltage drops below the under-voltage threshold (VPWRUV) output will turn off, FS will go to Logic [0], and the fault register UVF bit will be set to 1. Two cases need to be considered when the battery level recovers: * If output(s) command is (are) low, FS will go to Logic [1] but the UVF bit will remain set to 1 until the next read operation. * If the output command is ON, then FS will remain at Logic [0]. The output must be turned OFF and ON again to re-enable the state of output and release FS . The UVF bit will remain set to 1 until the next read operation. The under-voltage protection can be disabled through the SPI (bit UV_dis = 1). In this case, the FS and UVF bit do not
REVERSE BATTERY
The output survives the application of reverse voltage as low as -16V. Under these conditions, the output's gates are enhanced to keep the junction temperature less than 150C. The ON resistance of the output is fairly similar to that in the Normal mode. No additional passive components are required.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
GROUND DISCONNECT PROTECTION
In the event the 33988 ground is disconnected from load ground, the device protects itself and safely turns OFF the output regardless the state of the output at the time of Table 7. Device Behavior in Case of Under-voltage
High Side Switch (VPWR Battery Voltage)
disconnection. A 10K resistor needs to be added between the wake pin and the rest of the circuitry in order to ensure that the device turns off in case of ground disconnect and to prevent this pin to exceed its maximum ratings
State
UV Enable UV Enable UV Enable UV Enable IN = 0 IN = 0 IN = 1 IN = 1 (Falling VPWR) (Rising VPWR) (Falling VPWR) (Rising VPWR)
UV Disable IN = 0 (Falling or Rising VPWR)
UV Disable IN = 1 (Falling or Rising VPWR)
VPWR > VPWRUV
Output State FS State SPI Fault Register UVF Bit
OFF 1 0
OFF 1 1 until next read
ON 1 0
OFF 0 1
OFF 1 0
ON 1 0
VPWRUV > VPWR > UVPOR
Output State FS State SPI Fault Register UVF Bit
OFF 0 1
OFF 0 1
OFF 0 1
OFF 0 1
OFF 1 0
ON 1 0
UVPOR > VPWR > 2.5V
Output State FS State SPI Fault Register UVF Bit
OFF 1 1 until next read
OFF 1 1
OFF 1
OFF 1
OFF 1 0
ON 1 0
1 until next read 1 until next read
2.5V > VPWR > Output State 0V FS State SPI Fault Register UVF Bit Comments
OFF 1
OFF 1
OFF 1
OFF 1
OFF 1 0
OFF 1 0
1 until next read 1 until next read 1 until next read 1 until next read
UV fault is not latched
UV fault is not latched
UV fault is latched
Typical value; not guaranteed While VDD remains within specified range. = IN is equivalent to IN direct input or IN_spi SPI input.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
SPI PROTOCOL DESCRIPTION
The SPI interface has a full duplex, three-wire synchronous data transfer with four I/O lines associated with it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO), and Chip Select (CS). The SI / SO pins of the 33988 follow a first-in first-out (D7/ D0) protocol with both input and output words transferring the most significant bit (MSB) first. All inputs are compatible with 5.0 V CMOS logic levels. The SPI lines perform the following functions:
to D0. The internal registers of the 33988 are configured and controlled using a 4-bit addressing scheme, as shown in Table 8. Register addressing and configuration are described in Table 9. The SI input has an active internal pull-down, IDWN.
SERIAL OUTPUT (SO)
The SO data pin is a tri-stateable output from the shift register. The SO pin remains in a high-impedance state until the CS pin is put into a Logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, and the state of the key inputs. The SO pin changes states on the rising edge of SCLK and reads out on the falling edge of SCLK. Fault and Input Status descriptions are provided in Table 5.
SERIAL CLOCK (SCLK)
Serial clocks (SCLK) the internal shift registers of the 33988 device. The serial input (SI) pin accepts data into the input shift register on the falling edge of the SCLK signal while the serial output (SO) pin shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important that the SCLK pin be in a logic low state whenever CS makes any transition. For this reason, it is recommended that the SCLK pin be in a Logic [0] state whenever the device is not accessed (CS Logic [1] state). SCLK has an active internal pull-down, IDWN. When CS is Logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (highimpedance). See Figure 10 and Figure 11.
CHIP SELECT (CS)
The CS pin enables communication with the master microcontroller (MCU). When this pin is in a Logic [0] state, the device is capable of transferring information to, and receiving information from, the MCU. The 33988 device latches in data from the Input shift registers to the addressed registers on the rising edge of CS. The device transfers status information from the power output to the shift register on the falling edge of CS. The SO output driver is enabled when CS is Logic [0]. CS should transition from a Logic [1] to a Logic [0] state only when SCLK is a Logic [0]. CS has an active internal pull-up, IUP.
SERIAL INPUT (SI)
This is a serial interface (SI) command data input pin. SI instruction is read on the falling edge of SCLK. An 8-bit stream of serial data is required on the SI pin, starting with D7
CSB CS SCLK
SI
D7
D6
D5
D4
D3
D2
D1
D0
SO SO
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
NOTES:
Notes 1. RST is a ..., and D7 relate to the most recent ordered entry of data into the SPSS 2. D0, D1, D2, Logic [1] state during the above operation. 3. 2. D7:D0 relate..., and OD7 relate to the first 8 bits of ordered fault and status data out OD0, OD1, OD2, to the most recent ordered entry of data into the device. of the device. 3. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.
1.
RSTB is in a logic 1 state during the above operation. RST
Figure 10. Single 8-Bit Word SPI Communication
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
CSB
CS
SCLK SCLK SI
SI
D7 D6 D5 D2 D1 D0 D 7* D6* D 5* D 2* D 1* D0*
SSO O
OD7
OD6
OD5
OD2
OD1
OD0
D7
D6
D5
D2
D1
D0
NOTES:
. R T B is in lo s a RS Notes 1.1 RST Sis,Ta Logic,a [1]gai c d1 D tduringer thet thhee m b o v e e oc p e rt aot ir od ne .r e d e n t r y o f d a t a i n t o t h e S P S S state 7a tr ee l d u i n og above toperation. 2. D 0 D 1 , D 2 ..., n at t os r en . OD , O D 1 O D 2 ..., a n OD7 el 2.3 D7:D00relate ,,to the,, most d O D 7 rr orderedtt ht e ef i rf srtof 8b ibt si t so intodrtheddevice.n d ds tsat taut su sd a taat ao u tu o fo tf ht e ed e vPi cSeS. recent e par tee s teon entryi s 8 data fo o ro e reer e df af u lut l a a n 4. O D 0 , O D 1 O D 2 ..., a n d h t f d a t d ot h S 3. D7*:D0* relate to the previous 8 bits (last command word) of data that was previously shifted into the device. 4. OD7:OD0 relate to the F I G U R E 4 b ordered T I P L and b i t W Odata out ofCtheM M U N I C A T I O N first 8 bits of . M U L fault E 8 status R D S P I O device.
Figure 11. Multiple 8-Bit Word SPI Communication
SERIAL INPUT COMMUNICATION
SPI communication is accomplished using 8-bit messages. A message is transmitted by the MCU starting with the MSB, D7, and ending with the LSB, D0 (Table 8). Each incoming command message on the SI pin can be interpreted using the following bit assignments: the MSB (D7) is the watchdog bit and in some cases a register address bit common to both outputs or specific to an output; the next three bits, D6 : D4, are used to select the command register; and the remaining four bits, D3 : D0, are used to configure and control the outputs and their protection features. Multiple messages can be transmitted in succession to accommodate those applications where daisy chaining is desirable, or to confirm transmitted data, as long as the messages are all multiples of eight bits. Any attempt made to latch in a message that is not eight bits will be ignored. The 33988 has defined registers, which are used to configure the device and to control the state of the output. Table 9, summarizes the SI registers. The registers are addressed via D6 : D4 of the incoming SPI word (Table 8). Table 8. SI Message Bit Assignment
Bit Sig SI Msg Bit Message Bit Description
Table 9. Serial Input Address and Configuration Bit Map
SI Register D7 D6 D5 D4 Serial Input Data D3 D2 D1 D0
STATR OCR
s x
0 0 0 0 1 1 1 1 1 1
0 0 1 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0 0 1
0 CSNS1
EN
SOA2
SOA1
EN
SOA0
IN1_SPI CSNS0 IN0_SPI
SOCHLR s CDTOLR s DICR OSDR WDR NAR UOVR TEST s 0 1 0 1 x
SOCHs SOCL2s SOCL1s SOCL0s OL_DIS CD_DIS OCLT1s OCLT0 s s s FAST SR s 0 0 0 0 CSNS high s OSD2 0 0 0 IN DIS s OSD1 WD1 0 UV_dis A/Os OSD0 WD0 0 OV_dis
Freescale Internal Use (Test)
MSB
D7
Register address bit for output selection. Also used for Watchdog: toggled to satisfy watchdog requirements. Register address bits. Used to configure the inputs, outputs, and the device protection features and SO status content. Used to configure the inputs, outputs, and the device protection features and SO status content.
x = Don't care. s (SOA3 bit) = Selection of output: Logic [0] = HS0, Logic [1] = HS1.
D6 : D4 D3 : D1
LSB
D0
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Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
DEVICE REGISTER ADDRESSING
The following section describes the possible register addresses and their impact on device operation. Address x000 -- Status Register (STATR) The STATR register is used to read the device status and the various configuration register contents without disrupting the device operation or the register contents. The register bits D2:D0, determine the content of the first eight bits of SO data. When register content is specific to one of the two outputs, bit D7 is used to select the desired output (SOA3). In addition to the device status, this feature provides the ability to read the content of the OCR, SOCHLR, CDTOLR, DICR, OSDR, WDR, NAR, and UOVR registers. (Refer to the section entitled Serial Output Communication (Device Status Return Data).) Address x001 -- Output Control Register (OCR) The OCR register allows the MCU to control the outputs through the SPI. Incoming message bit D0 reflects the desired states of the high side output HS0 (IN0_SPI): a Logic [1] enables the output switch and a Logic [0] turns it OFF. A Logic [1] on message bit D1 enables the Current Sense (CSNS) pin. Similarly, incoming message bit D2 reflects the desired states of the high side output HS1 (IN1_SPI): Logic [1] enables the output switch and a Logic [0] turns it OFF. A Logic [1] on message bit D3 enables the CSNS pin. In the event that the current sense is enabled for both outputs, the current will be summed. Bit D7 is used to feed the watchdog if enabled. Address x010-- Select Over-current High and Low Register (SOCHLR) The SOCHLR register allows the MCU to configure the output over-current low and high detection levels, respectively. Each output is independently selected for configuration based on the state of the D7 bit; a write to this register when D7 is Logic [0] will configure the current detection levels for the HS0. Similarly, if D7 is Logic [1] when this register is written, HS1 is configured. Each output can be configured to different levels. In addition to protecting the device, this slow blow fuse emulation feature can be used to optimize the load requirements matching system characteristics. Bits D2 : D0 set the over-current low detection level to one of eight possible levels, as shown in Table 10. Bit D3 sets the over-current high detection level to one of two levels, which is described inTable 11.
Table 10. Over-current Low Detection Levels
SOCL2 (D2) SOCL1 (D1) SOCL0 (D0) Over-current Low Detection (Amperes)
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
12.5 11.25 10.0 8.75 7.5 6.25 5.0 3.75
Table 11. Over-current High Detection Levels
SOCH (D3) Over-current High Detection (Amperes)
0 1
50 37.5
Address x011 -- Current Detection Time and Open Load Register (CDTOLR) The CDTOLR register is used by the MCU to determine the amount of time the device will allow an over-current low condition before output latches OFF occurs. Each output is independently selected for configuration based on the state of the D7 bit. A write to this register when bit 7 is Logic [0] will configure the timeout for the HS0. Similarly, if D7 is Logic [1] when this register is written, then HS1 is configured. Bits D1: D0 allow the MCU to select one of four fault blanking times defined in Table 12. Note that these timeouts apply only to the over-current low detection levels. If the selected over-current high level is reached, the device will latch off within 20s. Table 12. Over-current Low Detection Blanking Time
OCLT [1:0] Timing
00 01 10 11
155ms 10ms 1.2ms 150s
A Logic [1] on bit D2 disables the over-current low (CD_dis) detection timeout feature. A Logic [1] on bit D3 disables the open load (OL) detection feature.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Address x100 -- Direct Input Control Register (DICR) The DICR register is used by the MCU to enable, disable, or configure the direct IN pin control of each output. Each output is independently selected for configuration based on the state of bit D7. A write to this register when bit D7 is Logic [0] will configure the direct input control for the HS0. Similarly, if D7 is Logic [1] when this register is written, then HS1 is configured. A Logic [0] on bit D1 will enable the output for direct control by the IN pin. A Logic [1] on bit D1 will disable the output from direct control. While addressing this register, if the input was enabled for direct control, a Logic [1] for the D0 bit will result in a Boolean AND of the IN pin with its corresponding D0 message bit when addressing the OCR register. Similarly, a Logic [0] on the D0 pin results in a Boolean OR of the IN pin with the corresponding message bits when addressing the OCR register. The DICR register is useful if there is a need to independently turn on and off several loads that are PWM'd at the same frequency and duty cycle with only one PWM signal. This type of operation can be accomplished by connecting the pertinent direct IN pins of several devices to a PWM output port from the MCU and configuring each of the outputs to be controlled via their respective direct IN pin. The DICR is then used to Boolean AND the direct IN(s) of each of the outputs with the dedicated SPI bit that also controls the output. Each configured SPI bit can now be used to enable and disable the common PWM signal from controlling its assigned output. A Logic [1] on bit D2 is used to select the high ratio (CSR1, 1/41000) on the CSNS pin for the selected output. The default value [0] is used to select the low ratio (CSR0, 1/20500). A Logic [1] on bit D3 is used to select the high speed slew rate for the selected output. The default value [0] corresponds to the low speed slew rate. Address 0101 -- Output Switching Delay Register (OSDR) The OSDR register configures the device with a programmable time delay that is active during Output ON transitions initiated via SPI (not via direct input). A write to this register configures both outputs for different delay. Whenever the input is commanded to transition from Logic [0] to Logic [1], both outputs will be held OFF for the time delay configured in the OSDR. The programming of the contents of this register have no effect on device Fail-safe mode operation. The default value of the OSDR register is 000, equating to no delay. This feature allows the user a way to minimize inrush currents, or surges, thereby allowing loads to be switched ON with a single command. There are eight selectable output switching delay times that range from 0ms to 525ms. Refer to Table 13.
Table 13. Switching Delay
OSD [2:0] (D2 : D0) Turn ON Delay (ms) Turn ON Delay (ms) HS0 HS1
000 001 010 011 100 101 110 111
0 75 150 225 300 375 450 525
0 0 150 150 300 300 450 450
Address 1101 -- Watchdog Register (WDR) The WDR register is used by the MCU to configure the watchdog timeout. Watchdog timeout is configured using bits D1:D0. When D1:D0 bits are programmed for the desired watchdog timeout period, the WD bit (D7) should be toggled as well, ensuring the new timeout period is programmed at the beginning of a new count sequence. Refer to Table 14. Table 14. Watchdog Timeout
WD [1:0] (D1: D0) Timing (ms)
00 01 10 11
620 310 2500 1250
Address 0110 -- No Action Register (NAR) The NAR register can be used to no-operation fill SPI data packets in a daisy chain SPI configuration. This allows devices to not be affected by commands being clocked over a daisy-chained SPI configuration, and by toggling the WD bit (D7), the watchdog circuitry will continue to be reset while no programming or data readback functions are being requested from the device. Address 1110 -- Under-voltage/Over-voltage Register (UOVR) The UOVR register can be used to disable or enable overvoltage and/or under-voltage protection. By default (Logic [0]), both protections are active. When disabled, an under-voltage or over-voltage condition fault will not be reported in the output fault register. Address x111 -- TEST The TEST register is reserved for test and is not accessible with the SPI during normal operation.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
SERIAL OUTPUT COMMUNICATION (DEVICE STATUS RETURN DATA)
When the CS pin is pulled low, the output status register is loaded. Meanwhile, the data is clocked out MSB- (OD7-) first as the new message data is clocked into the SI pin. The first eight bits of data clocking out of the SO, and following a CS transition, are dependant upon the previously written SPI word. Any bits clocked out of the SO pin after the first eight will be representative of the initial message bits clocked into the SI pin since the CS pin first transitioned to a Logic [0]. This feature is useful for daisy chaining devices as well as message verification. A valid message length is determined following a CS transition of Logic [0] to Logic [1]. If there is a valid message length, the data is latched into the appropriate registers. A valid message length is a multiple of eight bits. At this time, the SO pin is tri-stated and the fault status register is now able to accept new fault status information. The output status register correctly reflects the status of the STATR-selected register data at the time that the CS is pulled to a Logic [0] during SPI communication and / or for the period of time since the last valid SPI communication, with the following exceptions: * The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI communication never occurred. * Battery transients below 6.0V resulting in an undervoltage shutdown of the outputs may result in incorrect data loaded into the status register. The SO data transmitted to the MCU during the first SPI communication following an under-voltage VPWR condition should be ignored. * The RST pin transition from a Logic [0] to Logic [1] while the WAKE pin is at Logic [0] may result in incorrect data loaded into the status register. The SO data transmitted Table 15. Serial Output Bit Map Description
Previous STATR D7, D2, D1, D0 SOA3 SOA2 SOA1 SOA0 OD7 OD6 OD5
to the MCU during the first SPI communication following this condition should be ignored.
SERIAL OUTPUT BIT ASSIGNMENT
The 8 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 15 summarizes the SO register content. Bit OD7 reflects the state of the watchdog bit (D7) addressed during the prior communication. The value of the previous D7 will determine which output the status information applies to for the Fault (FLTR), SOCHLR, CDTOLR, and DICR registers. SO data will represent information ranging from fault status to register contents, user selected by writing to the STATR bits D2:D0. Note that the SO data will continue to reflect the information for each output (depending on the previous D7 state) that was selected during the most recent STATR write until changed with an updated STATR write. Previous Address SOA[2:0] = 000 If the previous three MSBs are 000, bits OD6 : OD0 will reflect the current state of the Fault register (FLTR) corresponding to the output previously selected with the bit OD7 (Table 16). Previous Address SOA[2:0] = 001 Data in bits OD1:OD0 contain CSNS0 EN and IN0_SPI programmed bits, respectively. Data in bits OD3:OD2 contain CSNS0 EN and IN0_SPI programmed bits, respectively. Previous Address SOA[2:0] = 010 The data in bit OD3 contain the programmed over-current high detection level (refer to Table 11), and the data in bits OD2:OD0 contain the programmed over-current low detection levels (refer to Table 12).
Serial Output Returned Data OD4 OD3 OD2 OD1 OD0
s x s s s 0 1 0 1 x
0 0 0 0 1 1 1 1 1 1
0 0 1 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0 0 1
s x s s s 0 1 0 1 -
OTFs 0 0 0 1 1 1 1 1 -
OCHFs 0 1 1 0 0 0 1 1 -
OCLFs 1 0 1 0 1 1 0 0 -
OLFs CSNS1 EN SOCHs OL_DIS s FSM_HS0 FSM_HS1 IN1 Pin - -
UVF IN1_SPI SOCL2s CD_DIS s OSD2 WDTO IN0 Pin - -
OVF CSNS0 EN SOCL1s OCLT1s IN DIS s OSD1 WD1 FSI Pin UV_dis -
FAULTs IN0_SPI SOCL0s OCLT0s A/O s OSD0 WD0 WAKE Pin OV_dis -
FAST SR s CSNS high s
s = Selection of output: Logic [0] = HS0, Logic [1] = HS1. x = Don't care.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Table 16. Fault Register
OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
Previous Address SOA[2:0] = 101 * SOA3 = 0. The returned data contain the programmed values in the OSDR. Bit OD3 (FSM_HS0) reflects the state of the output HS0 in the Fail-safe mode after a watchdog timeout occurs. * SOA3 = 1. The returned data contain the programmed values in the WDR. Bit OD2 (WDTO) reflects the status of the watchdog circuitry. If WDTO bit is Logic [1], the watchdog has timed out and the device is in Fail-safe mode. If WDTO is Logic [0], the device is in Normal mode (assuming the device is powered and not in Sleep mode), with the watchdog either enabled or disabled. Bit OD3 (FSM_HS1) reflects the state of the output HS1 in the Fail-safe mode after a watchdog timeout occurs. Previous Address SOA[2:0] = 110 * SOA3 = 0. OD3:OD0 return the state of the IN1, IN0, FSI, and WAKE pins, respectively (Table 17). Table 17. Pin Register
OD3 OD2 OD1 OD0
s
OTF
OCHFs OCLFs
OLFs
UVF
OVF
FAULTs
OD7 (s) = Selection of output: Logic [0] = HS0, Logic [1] = HS1. OD6 (OTF) = Over-temperature Flag. OD5 (OCHFs) = Over-current High Flag. (This fault is latched.) OD4 (OCLFs) = Over-current Low Flag. (This fault is latched.) OD3 (OLFs) = Open Load Flag. OD2 (UVF) = Under-voltage Flag. (This fault is latched or not latched.) OD1 (OVF) = Over-voltage Flag. OD0 (FAULTs) = This flag reports a fault and is reset by a read operation.
Note The FS pin reports a fault. For latched faults, this pin is reset by a new Switch ON command (via SPI or direct input IN).
Previous Address SOA[2:0] = 011 Data returned in bits OD1 and OD0 are current values for the over-current fault blanking time, illustrated in Table 12. Bit OD2 reports if the over-current detection timeout feature is active. OD3 reports if the open load circuitry is active. Previous Address SOA[2:0] =100 The returned data contain the programmed values in the DICR.
IN1 Pin
IN0 Pin
FSI Pin
WAKE Pin
* SOA3 = 1. The returned data contain the programmed values in the UOVR. Bit OD1 reflects the state of the under-voltage protection and bit OD0 reflects the state of the over-voltage protection. Refer to Table 15). Previous Address SOA[2:0] =111 Null Data. No previous register Read Back command received, so bits OD2:OD0 are null, or 000.
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TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
The 33988 can be configured in several applications. The figure below shows the 33988 in a typical main switch application.
VPWR VDD Voltage Regulator
VDD
VDD NC VPWR
VDD
VPWR
2.2k
10k
10
MCU
100nF 10F
2
VDD
VPWR
14
2.5F
10nF
I/O I/O SCLK CS I/O SI SO I/O A/D
1k
10k 10k 10k 10k 10k 10k
4 12 8 7 3 11 9 5 1 6
WAKE IN0 IN1 SCLK CS RST SO SI FS CSNS FSI
HS1
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15
HS0
16
LOAD GND
13
LOAD
RFS
The loads must be chosen in order to guarantee the device normal operating condition as junction temperature from -40 to 150C. In case of permanent short-circuit conditions, the duration and number of activation cycles must be limited with a dedicated MCU fault management using the fault reporting through SPI. Figure 13 describes the maximum turn-off current versus load inductance for single-pulse method, based on lab characterization results. When driving DC motor or Solenoid loads demanding multiple switching, an external recirculation device must be used to maintain the device in its Safe Operating Area.
Figure 12. Typical Applications Two application notes are available in order to: * propose safe configurations of the eXtreme Switch devices in case of application faults and protect all circuitry with minimum external components (AN 3274), * provide guidelines for Printed Circuit Board (PCB) design and assembly (AN 2469). Development effort will be required by the end users to optimize the board design and PCB layout in order to reach electromagnetic compatibility standards (emission and immunity).
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TYPICAL APPLICATIONS
Figure 13. Maximum Turn-off Current Versus Inductive Load (Single Pulse for RL = 0 and VPWR = 12 V at TJ = 150C Initial)
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PACKAGING SOLDERING INFORMATION
PACKAGING
SOLDERING INFORMATION
SOLDERING INFORMATION
The 33988 is packaged in a surface mount power package intended to be soldered directly on the printed circuit board. The 33988 was qualified in accordance with JEDEC standards JESD22-A113-B and J-STD-020A. The recommended reflow conditions are as follows:
* Convection: 225C +5 .0/ -0C * Vapor Phase Reflow (VPR): 215C to 219C * Infrared (IR) / Convection: 225C +5.0 / -0C The maximum peak temperature during the soldering process should not exceed 230C. The time at maximum temperature should range from 10s to 40s maximum.
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PACKAGING PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
For the most current revision of the package, visit www.freescale.com and perform a keyword search on 98ARL10521D.
PNA SUFFIX 16-PIN PQFN 98ARL10521D ISSUE C
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PACKAGING PACKAGE DIMENSIONS (CONTINUED)
PACKAGE DIMENSIONS (CONTINUED)
PNA SUFFIX 16-PIN PQFN 98ARL10521D ISSUE C
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REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
1.0 2.0
1/2007 5/2007
* Initial release * Changed typ and max number on Output Turn-ON Delay Time in Fast/Slow Slew Rate(20) * Changed min on Output Turn-OFF Delay Time in Fast Slew Rate Mode(21) * Changed labels on HS1 Switching Delay Time (OSD[2:0]) and HS0 Switching Delay Time (OSD[2:0]) * Corrected labels on Figure 12, Typical Applications * Updated Freescale format and style * Updated Junction-to-Ambient * Added Functional Internal Block Description * Updated Device Behavior in Case of Under-voltage * Added one paragraph and figure to Typical Applications
3.0
8/2007
4.0
11/2009
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MC33988 Rev. 4.0 11/2009

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